PARAMETER STUDY TO THE INTERPOSER STRESS ANALYSIS OF FINE PITCH 3-D STACK PACKAGE

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Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/34736

Title:	PARAMETER STUDY TO THE INTERPOSER STRESS ANALYSIS OF FINE PITCH 3-D STACK PACKAGE
Authors:	陳精一 Chen, Ching-I
Contributors:	機械工程學系 Mechanical Engineering
Keywords:	3-D STACK PACKAGE;TAGUCHI METHOD;TSV
Date:	2010
Issue Date:	2014-06-27 03:02:15 (UTC+8)
Abstract:	Through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite elem
Appears in Collections:	[Department of Mechanical Engineering] Seminar papers

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