Chung-Hua University Repository:Item 987654321/31961
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    Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/31961


    Title: Low-Cost Low-Power Bypassing-Based Multiplier Design
    Authors: 顏金泰
    YAN, JIN-TAI
    Contributors: 資訊工程學系
    Computer Science & Information Engineering
    Keywords: Low power;Multiplier
    Date: 2010
    Issue Date: 2014-06-27 01:40:05 (UTC+8)
    Abstract: Based on the simplification of the incremental adders instead of full adders in an array multiplier, a low-cost low-power bypassing-based multiplier is proposed. Compared with row-bypassing multiplier[7], column-bypassing multiplier[8] and 2-dimensional b
    Appears in Collections:[Department of Computer Science and Information Engineering] Seminar Papers

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