Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction

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Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/30989

Title:	Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction
Authors:	顏金泰 YAN, JIN-TAI
Contributors:	資訊工程學系 Computer Science & Information Engineering
Keywords:	Multi-bit flip-flop;Clock power
Date:	2013
Issue Date:	2014-06-27 01:17:07 (UTC+8)
Abstract:	Reducing the power consumption of a clock network is always one of critical issues in designing a high performance design. The concept of multi-bit flip–flop construction has been introduced by recent studies and shown the benefits of reducing clock power
Appears in Collections:	[Department of Computer Science and Information Engineering] Journal Articles

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