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    Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/37289


    Title: Reconfigurable VLSI Architecture for 9/7-5/3 Discrete Wavelet Transform
    Authors: 宋志雲
    Sung, Tze-Yun
    Contributors: 電子工程學系
    Electronics Engineering
    Keywords: DWT;reconfigurable architecture;low-power;high throughput;JPEG-2000
    Date: 2009
    Issue Date: 2014-07-01 10:19:40 (UTC+8)
    Abstract: In this paper, the high-efficient and reconfigurable architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on convolution scheme are proposed. The proposed parallel and pipelined architectures consist of a high-pass filter (HF) and a low-pa
    Appears in Collections:[Department of Microelectronics] Journal Articles

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