Multiplierless, Folded Reconfigurable Architecture for VLSI Wavelet Filter

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Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/33388

Title:	Multiplierless, Folded Reconfigurable Architecture for VLSI Wavelet Filter
Authors:	宋志雲 Sung, Tze-Yun
Contributors:	電子工程學系 Electronics Engineering
Keywords:	Folded reconfigurable architecture;9/7-5/3 discrete wavelet transform;DWT;high-pass filter;HF;low-pass filter;LF;convolution scheme
Date:	2010
Issue Date:	2014-06-27 02:22:07 (UTC+8)
Abstract:	In this paper, the high-efficient and reconfigurable architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on convolution scheme are proposed. The proposed parallel and pipelined architectures consist of a high-pass filter (HF) and a low-pa
Appears in Collections:	[Department of Microelectronics] Seminar Papers

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