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    Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/32052


    Title: Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
    Authors: 顏金泰
    YAN, JIN-TAI
    Contributors: 資訊工程學系
    Computer Science & Information Engineering
    Keywords: SiP design;Inter-die signal;3D IC
    Date: 2012
    Issue Date: 2014-06-27 01:43:05 (UTC+8)
    Abstract: Compared with the traditional flow for IC designs, the assignment of inter-die signals is an important stage in a die-stacking SiP design. In this paper, firstly, a connection graph for all the pads in a boundary stack can be constructed and a set of dyna
    Appears in Collections:[Department of Computer Science and Information Engineering] Seminar Papers

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