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    Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/32049


    Title: Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
    Authors: 顏金泰
    YAN, JIN-TAI
    Contributors: 資訊工程學系
    Computer Science & Information Engineering
    Keywords: Flip-flop;hold time;Setup time
    Date: 2013
    Issue Date: 2014-06-27 01:42:52 (UTC+8)
    Abstract: In a complex sequential circuit, the problem of fixing min-delay violations becomes more and more important. To our knowledge, no efficient approach is proposed to eliminate the min-delay violations in a layout-level implementation. In this paper, the min
    Appears in Collections:[Department of Computer Science and Information Engineering] Seminar Papers

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